1. Field
The present disclosure pertains to the field of processors. More particularly, the present disclosure pertains to a new instruction or a change to an instruction or an instruction set of a processor.
2. Description of Related Art
Computer architects often grapple with the difficulty of extending the instruction set of a processor. Often, instruction sets far outlive their originally contemplated lifespan because an installed base of software makes it profitable to maintain backward compatibility. Therefore, computer architects often add new instructions or new functionality to old instruction sets in order to provide new features yet maintain compatibility with the previously installed software base.
Adding new functionality to an existing instruction set can be a challenging exercise. Typically, an instruction set may have a set of mnemonics that translate into specific opcodes. The opcodes are binary values that are understood by the processor and which cause the processor to execute the intended instruction. Opcodes, however, are typically a particular length (i.e., a particular number of bits). Therefore, there are a finite number of instructions (i.e., 2N instructions for an N bit opcode) that may be represented by an opcode, depending on the number of bits dedicated to the opcode.
One common way to overcome this limitation is to use a “prefix”. One opcode may be designated as a prefix (rather than a particular instruction). The prefix indicates that a subsequent value or subsequent values should be decoded differently. In other words, the prefix changes the meaning of at least one subsequent instruction opcode. In some cases, prefixes may be used to define new instructions. In other cases, prefixes may be used to modify the behavior of existing instructions. For example, a prefix may temporarily override default address and/or operand sizes.
In the x86 instruction set, a prefix may be used to specify whether the opcode length is one or two bytes by use of the opcode expansion prefix. Therefore, by the use of prefixes, the total number of potential instructions can be increased. In some cases, a prefix may be used in conjunction with an escape code to define other instructions. In another case, a suffix may be used to specify additional instructions.
An additional limitation of an instruction set is that there may be a limited number of ways to specify operands. As such, there may a limitation on the number of operands that can be explicitly specified for an instruction. One way around this limitation is to implicitly specify where an instruction can find an additional operand by defining a location in the instruction definition, which is understood by the programmers using the instructions. For example, the MASKMOVQ instruction included in Intel's Pentium® Processor with MMX™ technology and subsequent Pentium® processors implicitly defines one of its operands to be located in a specified register. In this type of arrangement, a burden is placed on a programmer to move the appropriate operand into the specified location prior to execution of the instruction that uses that operand.
Another way to implicitly specify operands used in some instruction sets is to group registers together into pairs or quads. For instructions that operate on data which is a multiple of the register size, a single register may be specified and additional adjacent registers may be used to provide the additional operands. This technique has limited flexibility as well because all of the operands are accessed from the specific pre-defined locations in the register pair or quad.
Additional creative ways to provide additional functionality and/or flexibility to an instruction set would be beneficial.